Principal Engineer (Video Architect & Group Lead), nVIDIA
Senior Member, Institute of Electrical & Electronic Engineers (IEEE)
Adjunct Faculty, Santa Clara University
Pride and Joy 1
Pride and Joy 2
DESIGN: High-Performance Computer Architectures
DESIGN: VLSI Design of High-Speed Digital ASICs
DESIGN: Technology-Based Performance Analysis of Video Architectures
DESIGN: High-Speed CMOS Circuit Design and Analysis
CAD: Delay Modeling and Timing Simulation of Digital Circuits
CAD: Low-Power Issues at the Circuit Level
CAD: Performance-Driven Synthesis of Digital VLSI Systems
Click here for a select list of my publications.
World Clock
Google Scholar
Telephone on the Web
California Highway Info
Internal Revenue Service
Department of Motor Vehicles
Home Improvement Service Magic
US Citizenship and Immigration Services